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输入T72 回车
Begin Test 72
ASCII logging on
ASCII logging off
ASCII logging on
To get Gain in dB: divide it by sqrt(Ch1Gain*Ch2Gian)*2^16 and then convert to d
B
To Convert Phase Margin to Degree: (180/pi)*Atan(Phase/2^8)
freqStart=3480: freqStop=5496
GainMargin Limit=463930: PhaseMarginLimit=85
5112 468020 1098
5136 477109 1231
5160 494785 1385
5184 507639 1524
5208 520175 1968
5232 536435 2790
5256 556091 4843
5280 575076 29161
5304 582496 8428
5328 614782 2634
5352 628599 1592
5376 638765 1085
5400 635395 793
5424 618265 602
5448 582496 571
5472 586171 609
5496 611279 553
Head=0: Cylinder=0002C Status=1 Passed
5160 472586 1439
5184 481589 1595
5208 494785 1912
5232 503391 2422
5256 520175 3380
5280 536435 5641
5304 544382 16737
5328 571329 6630
5352 586171 2898
5376 600647 1807
5400 607755 1194
5424 604212 938
5448 582496 820
5472 593453 832
5496 621729 719
Head=0: Cylinder=0B1B8 Status=1 Passed
5160 468020 1284
5184 468020 1564
5208 477109 1719
5232 490426 1981
5256 494785 2408
5280 507639 3042
5304 524288 4915
5328 540423 7606
5352 552216 131965
5376 567558 7125
5400 582496 3022
5424 597061 1780
5448 593453 1465
5472 611279 1269
5496 625173 1021
Head=0: Cylinder=16344 Status=1 Passed
4632 468020 380
4656 472586 407
4680 481589 442
4704 499107 460
4728 503391 538
4752 499107 652
4776 481589 819
4992 468020 951
5064 477109 914
5088 494785 992
5112 507639 1125
5136 520175 1242
5160 536435 1470
5184 544382 1578
5208 567558 1938
5232 582496 2669
5256 604212 4168
5280 621729 10834
5304 648773 8349
5328 665117 2897
5352 681070 1704
5376 696657 1171
5400 693567 832
5424 671544 639
5448 638765 583
5472 638765 606
5496 665117 567
Head=1: Cylinder=0002C Status=1 Passed
4704 472586 471
4728 477109 522
4752 481589 638
5064 468020 873
5088 481589 988
5112 490426 1100
5136 499107 1231
5160 511852 1450
5184 511852 1666
5208 528368 1960
5232 544382 2395
5256 559939 3128
5280 578798 4943
5304 593453 31980
5328 614782 8295
5352 635395 3111
5376 648773 1857
5400 658628 1194
5424 638765 912
5448 628599 854
5472 645454 828
5496 665117 755
Head=1: Cylinder=0B1B8 Status=1 Passed
5088 472586 904
5112 481589 991
5136 490426 1148
5160 490426 1313
5184 490426 1470
5208 507639 1658
5232 511852 1871
5256 524288 2095
5280 540423 2767
5304 556091 5282
5328 567558 8451
5352 582496 37303
5376 600647 6676
5400 618265 2959
5424 625173 1832
5448 628599 1502
5472 645454 1287
5496 665117 1034
Head=1: Cylinder=16344 Status=1 Passed
freqStart=6984: freqStop=9000
GainMargin Limit=463930: PhaseMarginLimit=85
Head=0: Cylinder=0002C Status=0 Passed
Head=0: Cylinder=0B1B8 Status=0 Passed
Head=0: Cylinder=16344 Status=0 Passed
Head=1: Cylinder=0002C Status=0 Passed
Head=1: Cylinder=0B1B8 Status=0 Passed
Head=1: Cylinder=16344 Status=0 Passed
freqStart=9000: freqStop=10992
GainMargin Limit=463930: PhaseMarginLimit=85
passed代表过去了 fail代表测试失败 |
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